Method and apparatus for pipelined multiplexing employing analog delays for a multiport interface
US5592488A · kind A · utility
16Cited by
2References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Jan 7, 1997 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5647
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A multiport interface for digital communication systems having pipelined multiplexing of port instructions for increased throughput. The multiport interface includes an analog delay for independent timing of asynchronous operations, such as memory accesses. The multiport interface also has an instruction pipeline and multiplexer to coordinate a number of port instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.