Completely complementary MOS memory cell with tunneling through the NMOS and PMOS transistors during program and erase
US5594687A · kind A · utility
16Cited by
10References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 23, 1995 |
| Grant date | Jan 14, 1997 |
| Priority date | — |
| Expiry date | May 23, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuitry added to CMOS memory cell configured to enable tunneling through its PMOS and NMOS transistors, the circuitry preventing leakage current during programming. The circuitry includes a separate NMOS pass gate for connecting the source of the NMOS transistor of the CMOS cell to Vss. The gate of the NMOS pass gate is controlled to turn off the NMOS transistor during programming through the PMOS transistor to prevent current loss on the Vss line. The NMOS pass gate further provides a means for enabling or disabling the NMOS transistor making the CMOS cell useful as an array cell for a device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.