Configuration modes for a time multiplexed programmable logic device
US5600263A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 1995 |
| Grant date | Feb 4, 1997 |
| Priority date | — |
| Expiry date | Aug 18, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A PLD is operable in a variety of modes. In a first mode, the timeshare mode, the PLD remains at a single configuration for a plurality of user clock cycles. In a second mode, the logic engine mode, the PLD sequences through multiple configurations for each user cycle. In this mode, the period of time during which a configuration is active is called a micro cycle. In a third mode, the static mode, multiple configurations are programmed identically, so that the PLD performs the same function regardless of the configuration. Finally, the PLD is also operable in a combination mode, wherein part of the chip operates in one mode, for example, the static mode, and another part of the chip operates in the logic engine mode or the timeshare mode. In an alternative or co-existing embodiment, the PLD operates in one configuration mode during at least one user cycle and in another configuration mode during at least another user cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.