Auto-activate on synchronous dynamic random access memory
US5600605A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Feb 4, 1997 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronous dynamic random access memory (SDRAM) includes a memory array and is responsive to command signals and address bits. A command decoder/controller responds to selected command signals to initiate, at different times, a precharge command, an active command, and a transfer command. The command decoder/controller initiates the active command during the precharge command. Indicating circuitry responds to the precharge command to provide a precharge complete signal indicating the completion of a precharge command operation. A row address latch responds to the active command to receive and hold a value representing a row address of the memory array as indicated by the address bits provided at the time the active command is initiated, and responds to the precharge complete signal to release the row address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.