Method of fabricating a buried structure SRAM cell
US5602049A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 1994 |
| Grant date | Feb 11, 1997 |
| Priority date | — |
| Expiry date | Oct 4, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/904
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved SRAM cell having ultra-high density and methods for fabrication are described. Each SRAM cell, according to the present invention, has its own buried structure, including word lines (i.e., gate regions) and bit lines (i.e., source/drain regions), thus increasing the cell ratio of channel width of cell transistor to that of pass transistor to keep the data stored in the cell transistor more stable without increasing the area per cell. In addition, according to the present invention, the field isolation between active regions is not field oxide but blankly ion-implanted silicon substrate. Therefore, SRAM cells can be densely integrated due to the absence of bird's beak encroachment. Since the present invention has more planar topography, it is easily adapted to the VLSI process, which is always restricted by the limit of resolution of photolithography, thus increasing the degree of integration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.