Correction method leading to a uniform threshold voltage distribution for a flash eprom
US5608672A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 1995 |
| Grant date | Mar 4, 1997 |
| Priority date | — |
| Expiry date | Sep 26, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for correcting over-corrected memory cells in a flash EPROM. The flash EPROM includes an array of memory cells (25), where each of the cells includes a gate 18, a floating gate (16), a source (12), a drain (14), and a substrate (10). The method includes bulk erasing each of cells in the array of cells (step 40), which results in a plurality of over-erased cells. The over-erased cells are then corrected (step 42), which results in a plurality of over-corrected cells. The over-corrected cells are identified (step 44) and selectively erased (step 46), such that a uniform threshold voltage distribution (54) is provided for the cells in the flash EPROM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.