Semiconductor integrated circuit device
US5610856A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Mar 4, 1996 |
| Grant date | Mar 11, 1997 |
| Priority date | — |
| Expiry date | Mar 4, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/904
Abstract
An increase in the GND resistance and a drop in the resistance against electromigration are minimized when the ground voltage lines for shunting are finely constituted by using an Al wiring of the same layer as the pad layer, owing to the employment of a layout in which the arrangement of connection holes 24, 26 in a pad layer connected to one (data line) of the complementary data lines and the arrangement of connection holes in a pad layer connected to the other one (data line bar) of the complementary data lines, are inverted from each other every two bits of memory cells in the SRAM along the direction in which the complementary data lines extend.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.