Coherency and synchronization mechanisms for I/O channel controllers in a data processing system
US5613153A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 1994 |
| Grant date | Mar 18, 1997 |
| Priority date | — |
| Expiry date | Oct 3, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An I/O channel controller implements coherency and synchronization mechanisms, which allow the I/O channel controller to provide fully coherent direct memory access operations on a multiprocessor system bus, without implementing a retry protocol. This is made possible by performing delayed cache invalidates for real-time cache coherency conflicts between processors and I/O devices. Furthermore, I/O DMA writes occur real-time to the memory system and without the traditional Read With Intent to Modify (RWITM) operations. Completion of PIO operations has been coupled to the completion of I/O DMA writes operations in order to provide "seamless" I/O synchronization with respect to processor execution. An IOCC implementation has been described which benefits from those techniques by significantly reducing design complexity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.