Process and apparatus for etching metal in integrated circuit structure with high selectivity to photoresist and good metal etch residue removal
US5614060A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 23, 1995 |
| Grant date | Mar 25, 1997 |
| Priority date | — |
| Expiry date | Mar 23, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32139
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A process and apparatus are described for patterning a masked metal layer to form a layer of metal interconnects for an integrated circuits structure which removes metal etch residues, while inhibiting or eliminating erosion of the photoresist mask, by providing an amplitude modulation of the RF bias power supplied to the substrate support of the substrate being etched. The amplitude modulation of the RF power superimposes short pulses of RF power of sufficient magnitude (pulse height) and of sufficient duration (pulse width) to remove metal etch residues as they form during the etch process without, however, eroding the photoresist etch mask during the etch process sufficiently to adversely impact the patterning of the metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.