Method of fabricating junction termination extension structure for high-voltage diode devices
US5614421A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 27, 1994 |
| Grant date | Mar 25, 1997 |
| Priority date | — |
| Expiry date | Dec 27, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/981
Abstract
A method of fabricating high-voltage diode device on a silicon substrate which includes a first region and a second region is provided. The first and second regions having a first contact and a second contact area respectively. First, a first protective layer is formed on the first and second contact areas. A second protective layer is formed on the first protective layer and a portion of the first region adjacent to the first contact area. Next. Halogen ions are implanted into the first and second regions by using the second protective layer as a mask. The second protective layer is removed to expose unimplanted portion of the first region. Then, the first and second regions are oxidized to form a field oxide layer by using the first protective layer as a mask, wherein the unimplanted portion of the first region has a relatively lower oxidation rate and thereby a stepped part of the field oxide layer is formed over the first region. After removing the first protective layer, a first electrode plate is formed on the first contact area and the stepped part of the field oxide layer. A dielectric layer is formed overlying the first electrode plate and the field oxide layer. Finally, a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.