Two stage voltage level translator
US5614859A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 4, 1995 |
| Grant date | Mar 25, 1997 |
| Priority date | — |
| Expiry date | Aug 4, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and a voltage level translator circuit for driving a potential of an output node of the voltage level translator circuit to a pumped potential with minimal power consumption of the pump. Power is conserved by coupling the output node to a supply node through a first driver circuit and then driving the potential of the output node toward the supply potential. After the potential of the output node is pulled toward the supply potential the output node is decoupled from the supply node and coupled to the pumped supply node through a second driver circuit. The potential of the output node is then driven toward the pumped potential. In one embodiment a detector circuit of the invention monitors the first driver circuit and determines when to deactuate the first driver circuit and when to actuate the second driver circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.