Control gate-addressed CMOS non-volatile cell that programs through gates of CMOS transistors
US5615150A · kind A · utility
29Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 2, 1995 |
| Grant date | Mar 25, 1997 |
| Priority date | — |
| Expiry date | Nov 2, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved control gate-addressed CMOS memory cell is provided which allows for programming and erasing by tunneling through the gate oxides of the PMOS and NMOS transistors. The CMOS memory cell (400) includes a PMOS transistor (402), an NMOS transistor (403), and an NMOS pass transistor (405). A capacitor (430) has a first terminal coupled to a common floating gate (416) of the PMOS and NMOS transistors and has a second terminal coupled to a control gate node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.