Lead frame surface finish enhancement
US5616953A · kind A · utility
66Cited by
2References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 1, 1994 |
| Grant date | Apr 1, 1997 |
| Priority date | — |
| Expiry date | Sep 1, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An multiple lead semiconductor integrated circuit package incorporating a silicon die wire bonded to a lead frame plated by high purity copper. The die and the lead frame are encapsulated in an epoxy compound with lead fingers from the lead frame extending outside of the encapsulated compound. The high copper plating on the lead frame, which lead frame is not composed of high purity copper, increases the conductivity thereof so as to improve the signal speed for the lead frame. A thinner copper plating on the lead frame can be used without a decrease in signal speed as frequency of the signal is increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.