Flash EEPROM memory with improved discharge speed using substrate bias and method therefor
US5617357A · kind A · utility
79Cited by
4References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 7, 1995 |
| Grant date | Apr 1, 1997 |
| Priority date | — |
| Expiry date | Apr 7, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/972
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A floating gate cell memory device, such as an EPROM or flash EEPROM, with improved discharge speed. A negative bias is applied to the effective substrate during discharge. The negative bias increases the electric field near the junction, thereby increasing the number of hot holes which can be injected to the floating gate, improving discharge speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.