Method for forming residue free patterned conductor layers upon high step height integrated circuit substrates using reflow of photoresist

US5618384A · kind A · utility

Assignee

• Chartered Semiconductor Manufacturing LTD · SG

Inventors

• Lap Chan · Anaheim, US
• Met S. Zhou · Singapore, SG

Key dates

• Filing date: Dec 27, 1995
• Grant date: Apr 8, 1997
• Expiry date: Dec 27, 2015

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76838
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for forming a residue free patterned conductor layer upon a high step height integrated circuit substrate. First, there is provided a semiconductor substrate having formed thereon a high step height patterned integrated circuit layer. Formed upon the high step height patterned integrated circuit layer is a blanket conductor layer, and formed upon the blanket conductor layer is a patterned photoresist layer. The portions of the blanket conductor layer exposed through the patterned photoresist layer are etched through an anisotropic etch process to leave remaining a patterned conductor layer upon the surface of the high step height patterned integrated circuit layer and conductor layer residues at a lower step level of the high step height patterned integrated circuit layer. The patterned photoresist layer is then reflowed to cover exposed edges of the patterned conductor layer. Finally, the conductor layer residues at the lower step level of the high step height patterned integrated circuit layer are removed through an isotropic etch process.