Method for bypassing null-code sections for read-only memory by access line control
US5620915A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 1995 |
| Grant date | Apr 15, 1997 |
| Priority date | — |
| Expiry date | Jul 12, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The ROM device comprises a number of memory cells each is constructed based on a MOS transistor, the memory cells in the ROM are arranged into a number of rows and a columns. A number of word lines each connects to the gates of each of the MOS transistors of all the memory cells in each of the rows. A number of bit lines each connects to one of the source/drain pair of each of the MOS transistors of all the memory cells in each of the columns. A multiplexer comprises a number of transmitting transistors, each of the transmitting transistors is connected to a corresponding one of the bit lines, forming a current flow path including the transmitting transistor, the connected bit line, and the memory cells correspondingly connected to the bit line. A sense amplifier is coupled to the multiplexer for sensing the current flowing therethrough the current flow path to output a corresponding sense output signal. The method for bypassing null-code sections to comprise programing the transmitting transistor in the current flow path into an off status when all memory cells in the column connecting to the bit line of the transmitting transistor is required to contain null code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.