ESD protection circuit

US5623387A · kind A · utility

Assignee

• XILINX, INC. · US

Inventors

• Sheau-Suey Li · Cupertino, US
• Randy T. Ong · Cupertino, US
• Samuel Broydo · Los Altos Hills, US
• Khue Duong · San Jose, US

Key dates

• Filing date: Jun 5, 1995
• Grant date: Apr 22, 1997
• Expiry date: Jun 5, 2015

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/711

Abstract

An ESD protection circuit combines a split bipolar transistor with a transistor layout which exhibits very high tolerance to ESD events. The split bipolar transistor divides current among many segments and prevents the current hogging which often causes an ESD failure. Several splitting structures are disclosed, each combining a resistor in series with each segment to distribute current evenly. The transistor takes advantage of the snap-back effect to increase current carrying capacity. Layout positions metal contacts away from regions of highest energy dissipation. Layout also allows high currents to be dissipated through ESD protection structures and not through circuit devices such as output drivers or through parasitic bipolar transistors not designed for high current. Sharp changes in electron density are avoided by the use of high-diffusing phosphorus in N-regions implanted to both lightly and heavily doped levels. Critical corners are rounded rather than sharp. Certain P-type channel stop implants are positioned away from nearby N-regions to increase breakdown voltage.