Branch prediction cache with multiple entries for returns having multiple callers
US5623614A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 1993 |
| Grant date | Apr 22, 1997 |
| Priority date | — |
| Expiry date | Sep 17, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Branch Prediction Cache (BPC) selects from among multiple branch address entries for a single return-type instruction that returns to multiple callers. The BPC has a branch address associative memory, a return address associative memory, and word line logic used to validate and qualify entries. The branch address associative memory monitors program addresses for previously stored branch addresses. The return address stack (RtnStack) stores the return addresses for the most recent call-type instructions. The top of the stack is input to the return address associative memory. When a program address has multiple matches in the branch address associative memory, the return address associative memory enables only the entry that has an associated return address matching the top of the RtnStack. In an alternate embodiment, the return address associative memory is combined with a branch address cache and target address associative memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.