System and method for enabling and disabling a clock run function to control a peripheral bus clock signal
US5625807A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 1994 |
| Grant date | Apr 29, 1997 |
| Priority date | — |
| Expiry date | Sep 19, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/325
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for controlling a peripheral bus clock signal through a master and/or slave device is provided that accommodates a power conservation (or "clock run") scheme in which a peripheral bus clock signal may be stopped, for example, by a power management unit or other central resource. The clock run feature is enabled or disabled by the system during or immediately following system initialization, based upon the ability of the peripheral bus components to support the clock run feature. The system includes status and command registers to provide an indication of whether each of the peripheral bus devices can support the power conservation scheme. The status and command registers both include a bit dedicated to the clock run function. The status register bit is set based upon whether that particular device can support the clock run function. After each of the dedicated status register bits is checked, the dedicated command register bit is set in each of the peripheral bus devices to either enable or disable the clock run feature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.