Trenched DMOS transistor with buried layer for reduced on-resistance and ruggedness

US5629543A · kind A · utility

Assignee

• SILICONIX INCORPORATED · US

Inventors

• Fwu-Iuan Hshieh · Saratoga, US
• Mike F. Chang · Cupertino, US
• Lih-Ying Ching · Cupertino, US
• Sze Him Ng · Campbell, US
• William H. Cook · Fairport, US

Key dates

• Filing date: Aug 21, 1995
• Grant date: May 13, 1997
• Expiry date: Aug 21, 2015

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/393

Abstract

A trench DMOS transistor includes a buried layer region formed between the drain region and overlying drift region and having a doping type the same as that of the drift region and drain region. The buried layer region is more highly doped than the drain region or drift regions and is formed by e.g. implantation prior to epitaxial growth of the overlying drift region. By providing an optimized doping profile for the buried layer region, it is ensured that avalanche breakdown occurs at the buried layer region/body region. Thus drain-source on resistance is reduced because the JFET region present in prior art devices is eliminated, while device ruggedness and reliability are enhanced.