Cache coherency using flexible directory bit vectors
US5634110A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 1995 |
| Grant date | May 27, 1997 |
| Priority date | — |
| Expiry date | May 5, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2542
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller in a computer system is described. The memory controller maintains a directory comprising a plurality of entries. Each entry is associated with a memory block. The memory controller maintains an entry of the directory in a modified fine bit vector format when a memory block associated with the entry is cached in one or more nodes all of which are within a single partition of the computer system. The entry when maintained in the modified fine bit vector format comprises a partition field storing information identifying the single partition, and a modified fine bit vector field storing information identifying nodes in the single partition where the memory block is cached. The memory controller maintains the entry in a modified coarse bit vector format when the memory block is cached in multiple nodes distributed among P partitions of the computer system, where P is greater than one. The entry when maintained in the modified coarse bit vector format comprises Q partition fields each storing information identifying one of the P partitions, and Q modified coarse bit vector fields each storing information identifying nodes in one of the P partitions where the memory b…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.