Simplified dual damascene process for multi-level metallization and interconnection structure

US5635423A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Richard J. Huang · Cupertino, US
• Angela T. Hui · Fremont, US
• Robin Cheung · Cupertino, US
• Mark S. Chang · Los Altos, US
• Ming-Ren Lin · Cupertino, US

Key dates

• Filing date: Oct 11, 1994
• Grant date: Jun 3, 1997
• Expiry date: Oct 11, 2014

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76813
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor device containing an interconnection structure having a reduced interwiring spacing is produced by a modified dual damascene process. In one embodiment, an opening for a via is initially formed in a second insulative layer above a first insulative layer with an etch stop layer therebetween. A larger opening for a trench is then formed in the second insulative layer while simultaneously extending the via opening through the etch stop layer and first insulative layer. The trench and via are then simultaneously filled with conductive material.