Method for eliminating a false critical path in a logic circuit
US5638290A · kind A · utility
24Cited by
11References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 6, 1995 |
| Grant date | Jun 10, 1997 |
| Priority date | — |
| Expiry date | Apr 6, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49162
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for removing the critical false paths takes place during logic optimization. It is based on a path-constrained redundancy removal algorithm. This path-constrained redundancy removal algorithm automatically finds that a path node does not affect the behavior of the path output and so determines a critical path. This method is iteratively repeated for as long as this critical path is false.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.