Trenched DMOS transistor fabrication having thick termination region oxide
US5639676A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 1996 |
| Grant date | Jun 17, 1997 |
| Priority date | — |
| Expiry date | Feb 16, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/117
Abstract
A trenched DMOS transistor is fabricated using seven masking steps. One masking step defines both the P+ deep body regions and the active portions of the transistor which are masked using a LOCOS process. A second masking step defines the insulating oxide in the termination region. The insulating (oxide) layer in the termination region is thus thicker than in the active region of the transistor, thereby improving process control and reducing substrate contamination during processing. Additionally, the thicker field oxide in the termination region improves electric field distribution so that avalanche breakdown occurs in the cell (active) region rather than in the termination region, and thus breakdown voltage behavior is more stable and predictable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.