Overerase correction for flash memory which limits overerase and prevents erase verify errors
US5642311A · kind A · utility
45Cited by
6References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 24, 1995 |
| Grant date | Jun 24, 1997 |
| Priority date | — |
| Expiry date | Oct 24, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3445
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit including an array of flash EEPROM memory cells wherein overerase correction is provided after application of each erase pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.