Multiple tier collimator system for enhanced step coverage and uniformity
US5643428A · kind A · utility
32Cited by
8References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 1, 1995 |
| Grant date | Jul 1, 1997 |
| Priority date | — |
| Expiry date | Feb 1, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J37/34
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A collimator system for use in PVD sputtering of semiconductor wafers having multiple tiers provided between a target and wafer substrate. The collimator system prevents target atoms from contacting the wafer at substantially oblique angles, thereby providing good step coverage uniformity over the surface of the wafer. Additionally, the presence of more than one tier prevents localized build-up of target atoms that occurs in conventional single tier collimators, thereby providing good flat coverage uniformity over the surface of the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.