Method for forming trench-isolated FET devices
US5643822A · kind A · utility
46Cited by
9References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 10, 1995 |
| Grant date | Jul 1, 1997 |
| Priority date | — |
| Expiry date | Jan 10, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76237
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for improving the subthreshold leakage characteristics of a trench-isolated FET device is described. This method involves first forming a vertical slot within a stack structure disposed on an oxide-covered silicon substrate, and then forming spacers on the sidewalls of the slot. A trench is then etched in the substrate. Removal of the spacers uncovers a horizontal ledge on the exposed surfaces of the oxide-covered substrate, adjacent the trench. The ledge is then perpendicularly implanted with a suitable dopant, thereby suppressing edge conduction in the device. Articles prepared by this method are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.