Program algorithm for low voltage single power supply flash memories
US5644531A · kind A · utility
55Cited by
2References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 1, 1995 |
| Grant date | Jul 1, 1997 |
| Priority date | — |
| Expiry date | Nov 1, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programming algorithm for a flash memory wherein programming circuitry is subdivided into a set of separately controllable groups. The algorithm detects a number of logic zeros to be programmed into a flash cell array by each group and switches among the groups such that a number of simultaneously programmed cells in the flash cell array does not exceed a predetermined number and such that maximum available programming current is used to enhance programming speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.