Processor with single clock decode architecture employing single microROM
US5644741A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 1993 |
| Grant date | Jul 1, 1997 |
| Priority date | — |
| Expiry date | Oct 18, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes storage circuitry for storing an instruction and memory circuitry addressable by a microaddress for outputting a microinstruction in response to the microaddress. The processor further includes sequencing circuitry coupled to provide the microaddress to the memory circuitry. Finally, the processor includes decode circuitry coupled to the storage circuitry for detecting whether the instruction stored in the storage circuitry comprises a single clock instruction before the memory circuit outputs the microinstruction, and for indicating to the sequencing circuitry in response to detecting whether the instruction stored in the storage circuitry comprises a single clock instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.