Fast, dual ported cache controller for data processors in a packet switched cache coherent multiprocessor system
US5644753A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 1996 |
| Grant date | Jul 1, 1997 |
| Priority date | — |
| Expiry date | Sep 17, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor computer system has data processors and a main memory coupled to a system controller. Each data processor has a cache memory. Each cache memory has a cache controller with two ports for receiving access requests. A first port receives access requests from the associated data processor and a second port receives access requests from the system controller. All cache memory access requests include an address value; access requests from the system controller also include a mode flag. A comparator in the cache controller processes the address value in each access request and generates a hit/miss signal indicating whether the data block corresponding to the address value is stored in the cache memory. The cache controller has two modes of operation, including a first standard mode of operation in which read/write access to the cache memory is preceded by generation of the hit/miss signal by the comparator, and a second accelerated mode of operation in which read/write access to the cache memory is initiated without waiting for the comparator to process the access request's address value. The first mode of operation is used for all access requests by the data processor an…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.