Threshold adjustment in field effect semiconductor devices

US5648288A · kind A · utility

Assignee

• SILICONIX INCORPORATED · US

Inventors

• Richard K. Williams · Cupertino, US
• Michael E. Cornell · Campbell, US

Key dates

• Filing date: Jul 27, 1994
• Grant date: Jul 15, 1997
• Expiry date: Jul 27, 2014

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/307

Abstract

A process for fabricating both CMOS and LDMOS transistors includes a high temperature, long diffusion subsequent to deposition of the polysilicon gate for forming MOSFET body regions. Similarly, a process for fabricating both CMOS and NPN transistors includes a high temperature, long diffusion subsequent to deposition of the polysilicon gate for forming NPN base regions. In both processes, the threshold voltage of the PMOS devices is adjusted subsequent to both gate formation and the high temperature, long diffusions by implanting a suitable dopant into the PMOS channel through the gate. Since the gate is formed prior to threshold adjust, high temperature processing and long diffusions requiring the presence of the gate are completed without adversely affecting the adjusted threshold voltage. The p+ source/drain implant mask can be used to restrict the threshold adjust implant to the PMOS devices, thereby avoiding adversely affecting other devices in the integrated circuit. The p+ source/drain implant mask can also be used to protect the gates of some of the PMOS devices, thereby fabricating two classes of PMOS devices, one being threshold adjusted and the other not being threshold…