Plasma damage reduction device for sub-half micron technology
US5650651A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 12, 1996 |
| Grant date | Jul 22, 1997 |
| Priority date | — |
| Expiry date | Apr 12, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved transistor structure. The novel transistor structure includes a substrate, at least one source disposed on the substrate; at least one drain disposed on the substrate; and at least one gate disposed on the substrate between the source and the drain. The gate has a layer of at least partially conductive material of area A.sub.g. The gate is connected to a pad provided by a single or multiple layer of conductive material of area A.sub.p. In accordance with the present teachings, a thin gate oxide capacitor of area A.sub.c is connected to the gate pad via single or multiple layer of conductive material. The area of the third layer is selected such that the ratio R of the area of the second layer A.sub.p to the area of the first layer A.sub.g plus the area of the third layer A.sub.c is equal to a predetermined number. The third layer serves to reduce the antenna effect created by the pad and the multiple layers of conductive material between the gate contact and the pad in accordance with the antenna ratio R.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.