Temperature compensated reference for overerase correction circuitry in a flash memory
US5650966A · kind A · utility
20Cited by
1References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 1, 1995 |
| Grant date | Jul 22, 1997 |
| Priority date | — |
| Expiry date | Nov 1, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reference circuit for overerase correction in a flash memory includes a reference flash memory cell biased in a substantially similar manner to that of an overerased flash memory cell. The leakage current for the reference flash memory cell is preset to a tolerable level of leakage current for a maximum operating temperature of the flash memory and the reference flash memory cell tracks the temperature characteristics of the overerased flash memory cell, to avoid costly overcorrection at high temperatures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.