Repairable chip bonding/interconnect process
US5653019A · kind A · utility
40Cited by
6References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 1995 |
| Grant date | Aug 5, 1997 |
| Priority date | — |
| Expiry date | Aug 31, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.