Programmable computer system element with built-in self test method and apparatus for repair during power-on
US5659551A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 1995 |
| Grant date | Aug 19, 1997 |
| Priority date | — |
| Expiry date | Dec 14, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Computer system element has a VLSI array with redundant areas and an ABIST (Array Built-In Self Test) system having mirror image fuse registers enabling scan of failed addresses to be used to replace hardware errors detected during power-on at a customer location. The ABIST controller allows self test functions (e.g. test patterns, read/write access, and test sequences) to be modified without hardware changes to the test logic. Test sequence is controlled by logical test vectors, which can be changed, making the task of developing complex testing sequences relatively easy and useful for enabling array self-tests to be performed in a customer's office at power-on reset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.