Method of fabricating compliant interface for semiconductor chip
US5659952A · kind A · utility
367Cited by
20References
48Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 1994 |
| Grant date | Aug 26, 1997 |
| Priority date | — |
| Expiry date | Dec 29, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49174
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and an apparatus for providing a planar and compliant interface between a semiconductor chip and its supporting substrate to accommodate for the thermal coefficient of expansion mismatch therebetween. The compliant interface is comprised of a plurality of compliant pads defining channels between adjacent pads. The pads are typically compressed between a flexible film chip carrier and the chip. A compliant filler is further disposed within the channels to form a uniform encapsulation layer having a controlled thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.