Method of encapsulating die and chip carrier
US5663106A · kind A · utility
136Cited by
17References
47Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 19, 1994 |
| Grant date | Sep 2, 1997 |
| Priority date | — |
| Expiry date | May 19, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49146
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of packaging a semiconductor chip assembly includes the encapsulation of the same after establishing an encapsulation area and providing a physical barrier for protecting the terminals of a chip carrier. An alternative or supplement to providing a physical barrier is to provide a preform of an encapsulation material which includes a predetermined volume of such material so that only the encapsulation area is filled. For a semiconductor chip assembly which does not yet have an elastomeric layer, a method of simultaneously forming such an elastomeric layer and encapsulating a semiconductor chip assembly is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.