Fet device with double spacer
US5663586A · kind A · utility
35Cited by
6References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 25, 1996 |
| Grant date | Sep 2, 1997 |
| Priority date | — |
| Expiry date | Apr 25, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/90
Abstract
An improved FET device in which the hot carrier immunity and current driving capability are improved, and the subthreshold leakage current is minimized. The device has a gate electrode with vertical sidewalls, and a thin layer of SiO.sub.2 over the electrode. A first polysilicon spacer is provided on the vertical sidewalls, with a second overlying oxide spacer over the first spacer. The top portion of the SiO.sub.2 layer between the gate electrode and the polysilicon spacer is made conductive enough to keep the gate electrode and the polysilicon spacer at the same potential. Lightly doped source and drain regions are provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.