Nonvolatile memory blocking architecture
US5663923A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 1995 |
| Grant date | Sep 2, 1997 |
| Priority date | — |
| Expiry date | Apr 28, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory includes a global line and a first block and a second block. The first block includes a plurality of first local lines and a first local decoder coupled to the global line and the first local lines for selectively coupling the global line to one of the first local lines in accordance with an address when the first local decoder is enabled and for isolating the first local lines from the global line when the first local decoder is disabled. The second block includes a plurality of second local lines and a second local decoder coupled to the global line and the second local lines for selectively coupling the global line to one of the second local lines in accordance with the address when the second local decoder is enabled and for isolating the second local lines from the global line when the second local decoder is disabled such that interference between the first and second blocks is eliminated during memory operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.