Interactive time-driven method of component placement that more directly constrains critical paths using net-based constraints
US5666290A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 1995 |
| Grant date | Sep 9, 1997 |
| Priority date | — |
| Expiry date | Dec 27, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of optimizing the placement of components of an integrated circuit to ensure that all circuit paths will meet their timing criteria, as well as to minimize area and total wire length is disclosed. The method employs a non-constant net weighting distribution along critical paths to encourage a mincut algorithm to place components so that path lengths are minimized as well as the entire nets coupled to paths. The magnitude of weights assigned are commensurate with the slack the path has with respect to its maximum delay constraint, as well as the level of method iteration. Any nets not deemed critical are assigned a minimum capacitance constraint to prevent them from becoming critical as a function of actual placement. Weights assigned to capacitively constrained nets are inversely proportional to the difference between the maximum capacitance allowed and the estimated capacitance of the current placement. A novel manner of estimating the propagation delay along the interconnect of the critical path is implemented. A novel weighting of driver/buffer pairs ensure that the most sensitive nets of the pairs are kept short.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.