Memory cell for a programmable logic device (PLD) avoiding pumping programming voltage above an NMOS threshold
US5666309A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 1995 |
| Grant date | Sep 9, 1997 |
| Priority date | — |
| Expiry date | Nov 17, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell for a programmable logic device (PLD) and method for programming the memory cell. The memory cell includes components typically found in a memory cell for a PLD including an NMOS transistor having a floating gate, and two capacitors coupled to the floating gate, one capacitor being a tunneling capacitor enabling charge to be added to and removed from the floating gate. The memory cell further includes an NMOS pass gate transistor for supplying charge to the tunneling capacitor, but unlike conventional NMOS pass gates, it has a reduced threshold so that during programming when a programming voltage is applied to its drain, it can be turned on with an identical programming voltage applied to its gate, rather than requiring that its gate voltage be pumped above its drain voltage during programming. The reduced threshold can be obtained by removing the vt implant and punch through implant normally provided in its channel, or by other means.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.