Fail-safe communication abort mechanism for parallel ports with selectable NMI or parallel port interrupt
US5666559A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 1996 |
| Grant date | Sep 9, 1997 |
| Priority date | — |
| Expiry date | Oct 9, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0793
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system is provided including a processor and a parallel port configured to transfer data to or from a peripheral device. The parallel port includes a data buffer for receiving data transferred on a system bus when the processor executes a write cycle to the parallel port. A control unit associated with the parallel port decodes the address signals of the system bus to selectively latch data within the data buffer, and generates handshake signals to the peripheral device to indicate that write data is presently contained within the data buffer. The peripheral device consequently receives the data and provides an acknowledge signal to the control unit. The control unit thereafter generates a ready signal to indicate to the processor that the data has been written into the peripheral device. A time-out counter is coupled to the control unit to determine whether the peripheral device has returned the acknowledge signal within a predetermined time-out period after the control unit asserts the handshake signal to the peripheral device indicating that data is available at the parallel port. If the time-out period expires and the peripheral device did not return an acknowledge s…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.