Dual poly-gate deep submicron CMOS with buried contact technology

US5670397A · kind A · utility

Assignee

• POWERCHIP SEMICONDUCTOR CORP. · TW

Inventors

• Yih-Jau Chang · Cupertino, US
• Shye-Lin Wu · 東區, TW

Key dates

• Filing date: Jan 16, 1997
• Grant date: Sep 23, 1997
• Expiry date: Jan 16, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0177

Abstract

A CMOS device with buried contacts is formed using a polysilicon stack layer and twin-well and liquid phase deposition (LPD) processes. A gate oxide layer and a first polysilicon layer are formed on a substrate. Then the gate oxide and first polysilicon layer are etched to form gate structures. A polysilicon stack layer is formed on the gate structures. The polysilicon stack layer and the first polysilicon layer are anisotropically dry etched, forming first trenches that expose portions of the gate oxide and portions of the substrate defining S/D regions for a NMOSFET. A NMOS lightly doped drain (LDD) with halo doping profile is implanted. A first LPD oxide is selectively formed in the first trenches. Subsequently, a first heavy ion implantation is performed into the polysilicon stack layer for forming the source, drain, gate and buried contacts of the NMOSFET. Trenches are formed in the polysilicon stack layer and first polysilicon layer to define S/D regions and buried contacts for a PMOSFET. A PMOS LDD with halo doping profile is implanted. A second LPD oxide is selectively formed in the second trenches. A second heavy ion implantation is performed into the polysilicon stack lay…