Method of forming multiple gate oxide thicknesses on a wafer substrate
US5672521A · kind A · utility
65Cited by
5References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 21, 1995 |
| Grant date | Sep 30, 1997 |
| Priority date | — |
| Expiry date | Nov 21, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/981
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device and manufacturing process wherein a first region is formed in a substrate with a dopant that enhances oxide formation and a second region is formed in the substrate with a dose of nitrogen that retards oxide formation. An oxide layer is grown over the first and the second regions and over a third region of the substrate such that the first, second, and third regions yield differing thicknesses of the oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.