Processor having primary integer execution unit and supplemental integer execution unit for performing out-of-order add and move operations
US5675758A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 1994 |
| Grant date | Oct 7, 1997 |
| Priority date | — |
| Expiry date | Nov 15, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3893
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The existing execution units of a high-performance processor are augmented by the addition of a supplemental integer execution unit, termed the Add/Move Unit (AMU), which performs select adds and moves in parallel and out-of-order with respect to the other execution units. At small incremental cost, AMU enables better use of the expensive limited resources of an existing Address Preparation unit (AP), which handles linear and physical address generation for memory operand references, control transfers, and page crosses. AMU removes data dependencies and thereby increases the available instruction level parallelism. The increased instruction level parallelism is readily exploited by the processor's ability to perform out-of-order and speculative execution, and performance is enhanced as a result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.