Semiconductor chip package
US5677566A · kind A · utility
376Cited by
12References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 8, 1995 |
| Grant date | Oct 14, 1997 |
| Priority date | — |
| Expiry date | May 8, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip package that includes discrete conductive leads in electrical contact with bond pads on a semiconductor chip. This chip/lead assembly is encapsulated within an encapsulating material and electrode bumps are formed through the encapsulating material to contact the conductive leads. The electrode bumps protrude from the encapsulating material for connection to an external circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.