Processor and method for managing execution of an instruction which determine subsequent to dispatch if an instruction is subject to serialization
US5678016A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 1995 |
| Grant date | Oct 14, 1997 |
| Priority date | — |
| Expiry date | Aug 8, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/384
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are disclosed for managing the execution of a floating-point store instruction within a data processing system including a memory and a superscalar processor having a number of floating-point registers (FPRs). According to the present invention, multiple instructions are dispatched for execution by the processor, including a floating-point store instruction having as an operand the content of a particular FPR. A determination is made whether the particular FPR is a destination register for results of a second instruction which precedes the store instruction in program order. If so, a determination is made whether the second instruction must complete before subsequent instructions can be successfully dispatched. In response to a determination that the second instruction must be completed prior to successfully dispatching subsequent instructions, the floating-point instruction is cancelled and redispatched after the completion of the second instruction. In response to a determination that the second instruction need not be completed prior to successfully dispatching subsequent instructions, execution of the floating-point store instruction is initiated by compu…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.