Computer system employing an enable line for selectively adjusting a peripheral bus clock frequency
US5678065A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 1994 |
| Grant date | Oct 14, 1997 |
| Priority date | — |
| Expiry date | Sep 19, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/423
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system is described for facilitating operation of a peripheral bus, such as a PCI bus, at different clock frequencies. One embodiment includes an enable line (66 MHzENABLE) connected to each of the devices resident on the PCI bus. The enable line is passively pulled high through a pull-up resistor if all devices resident on the PCI bus can support high frequency operation (such as, for example, 66 MHz). If any device cannot support high frequency operation, the device internally connects the enable line to ground in accordance with present industry specifications. Thus, the enable line will be passively high only if all of the PCI devices support high frequency operation, but will be asserted low if any device cannot support high frequency operation. The invention also includes a dedicated status bit to permit the system to warn the operator of discrepancies between device and bus capabilities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.