Method for narrowing threshold voltage distribution in a block erased flash memory array
US5680350A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 14, 1994 |
| Grant date | Oct 21, 1997 |
| Priority date | — |
| Expiry date | Dec 14, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention constitutes a method for narrowing threshold voltage distribution among the individual cells of a block erased flash memory array by firstly, preprogramming cells within the block be erased to a level of saturation using hot electron injection to drive a surplus of electrons into the floating gate of each cell; secondly, subjecting all cells with the block to a first erase pulse which causes the surplus electrons within the floating gate of each cell to be driven into the cell's source region via Fowler-Nordheim tunneling, with the erase pulse being of sufficient length to erase every cell within the block; thirdly, subjecting all cells within the block to a word line stress step or a soft programming step, by means of which some electrons are driven back into the floating gate of each cell via Fowler-Nordheim tunneling or hot electron injection, respectively; and, fourthly, subjecting all cells within the block to a second erase pulse, the second erase pulse being at least an order of magnitude shorter than the first erase pulse. Use of the second erase pulse following the word line stress step not only shifts the threshold voltage distribution to a somewhat lower l…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.