Method and system for testing memory programming devices
US5682472A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 1995 |
| Grant date | Oct 28, 1997 |
| Priority date | — |
| Expiry date | Mar 17, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3191
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A novel system and method for testing semiconductor devices has a pattern generator implementing a test signal algorithm uniquely coupled with a recording system which is an individual hardware system for each device under test. The improved pattern generator and recording system functions in conjunction with a system designed to perform parallel test and burn-in of semiconductor devices, such as the Aehr Test MTX System. The MTX can functionally test large quantities of semiconductor devices in parallel. It can also compensate for the appropriate round trip delay value for each chip select state for each device under test. This system of testing provides an effective and practical method for reducing overall test cost without sacrificing quality.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.